AMD’s Next-Gen Zen 6 CPU ISA Revealed in Latest GCC Compiler Support
AMD’s upcoming Zen 6 CPU Instruction Set Architecture (ISA) has been unveiled through new support added to the GCC compiler. A recent patch titled “Add AMD znver6 processor support” not only introduces compatibility for AMD’s next-generation Zen 6 core architecture but also reveals some key features of its initial ISA.
New ISA Enhancements for Zen 6
The patch discloses the following new ISA additions for the Zen 6 core:
- AVX512_FP16
- AVX_NE_CONVERT
- AVX_IFMA
- AVX_VNNI_INT8
While AMD’s existing Zen architectures already support AVX-512 instructions, the introduction of AVX-512 FP16 will further enhance the computational capabilities of future Zen processors. Additionally, support for VNNI INT8 instructions will improve AI and machine learning workloads.
Zen 6 CPU Identification and Family Variants
In a separate discovery, popular hardware analyst @InstLatX64 has identified a new Zen 6 CPU ID: B80F00. This ID likely corresponds to one of the multiple Zen 6 families in development.
Zen 6 is expected to include server-grade Venice lineups, offered in two variants: Classic and Dense. The details are as follows:
- Venice Classic:
- SP7 SKUs: “B50F00”
- SP8 SKUs: “B90F00”
- Up to 12 cores per CCX
- Venice Dense:
- SP7 SKUs: “BC0F00”
- SP8 SKUs: “BA0F00”
- Up to 32 cores per CCX
The Venice lineup is expected to scale up to 256 cores, which translates to 8 Core Complexes (CCXs). Each CCX on the Dense line carries 128 MB of L3 cache, totaling up to 1024 MB of L3 cache — a significant increase suited for high-performance server workloads.
Client-Focused Zen 6 Families
Beyond the server products, at least four client families will adopt the Zen 6 core architecture:
- Olympic Ridge — High-end AM5 platform with up to 24 cores and 48 threads (featuring 12 cores and 48 MB L3 cache per CCX)
- Gator Range
- Medusa Point
- Medusa Halo
The multi-chip module (MCM) designs among these families are set to utilize TSMC’s advanced N2P process node. For monolithic chips, such as those expected in the Medusa Point and Gator Range APU lines, TSMC’s N3P and N3C nodes will likely be employed.
What’s Next for Zen 6?
AMD’s Financial Analyst Day is only days away, which may include early teasers about Zen 6. However, official announcements and product launches are anticipated to begin at CES 2026. Stay tuned for more updates as this exciting new architecture approaches release.
AMD Zen CPU/APU Roadmap Overview
Below is a summary table showcasing the progression of AMD’s Zen architecture across various product lines and process nodes:
| Generation | Core Codename | Process Node | Server | High-End Desktop | Mainstream Desktop CPUs | Enthusiast Mobile CPUs | Desktop Notebook APUs | Low-Power Mobile |
|---|---|---|---|---|---|---|---|---|
| Zen 7 | Monarch | TBA | TBA | TBA | TBA | TBA | TBA | TBA |
| Zen 6C | Morpheus | 3nm / 2nm? | EPYC Venice (6th Gen) | Ryzen Threadripper 9000 (Shamida Peak) | Ryzen **** (Olympic Ridge) | Ryzen **** (Gator Range) | Ryzen AI 400 (Medusa Point / BB) | Ryzen *** (Escher) |
| Zen 6 | Nirvana (Zen 5) | 3nm / 2nm? | EPYC Venice (6th Gen) | Ryzen Threadripper 7000 (Storm Peak) | Ryzen 9000 (Granite Ridge) | Ryzen 9000HX (Fire Range) | Ryzen AI 500 (Sound Wave)? | Ryzen 7000 (Mendocino) |
| Zen 5 (C) | Prometheus (Zen 5C) | 3nm | EPYC Turin (5th Gen) | N/A | Ryzen 7000 (Raphael) | Ryzen 7000HX (Dragon Range) | Ryzen AI 500 (TBA) | TBA |
| Zen 4 (C) | Persphone (Zen 4) / Dionysus (Zen 4C) | 4nm | EPYC Genoa (4th Gen) / EPYC Siena (4th Gen) / EPYC Bergamo (4th Gen) | Ryzen Threadripper 5000 (Chagal) | Ryzen 6000 (Warhol / Cancelled) | N/A | Ryzen AI 400 (Medusa Point / BB) | Ryzen 6000 (Dragon Crest) |
Source
Information compiled from reports by @InstLatX64 and official GCC compiler patch notes.
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Stay tuned to our site for the latest news and detailed coverage as AMD’s Zen 6 architecture continues to unveil new advancements and capabilities.
https://wccftech.com/amd-zen-6-cpu-core-isa-revealed-avx512-fp16-vnni-int8-more/
